Commits · main · Malte Munch / d0011e_lab2_veryl

Apr 09, 2025
- Replace some more VHDL occurences with Veryl · a081adff
  Malte Munch authored 1 week ago
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Signed-off-by: Malte Munch <malte.munch@ltu.se>
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  a081adff
Apr 03, 2025
- README · b675fc61
  Malte Munch authored 1 week ago
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Signed-off-by: Malte Munch <malte.munch@ltu.se>
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  b675fc61
- Part3 · 943476d2
  Malte Munch authored 2 weeks ago
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Signed-off-by: Malte Munch <malte.munch@ltu.se>
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  943476d2
- Part1,2,5 Done · d967c20b
  Malte Munch authored 2 weeks ago
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Signed-off-by: Malte Munch <malte.munch@ltu.se>
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  d967c20b
Apr 02, 2025
- and another beautiful commit to save my precious work · ac7ba202
  Malte Munch authored 2 weeks ago
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Signed-off-by: Malte Munch <malte.munch@ltu.se>
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  ac7ba202
- little intermediate commit :) · 2e3e4933
  Malte Munch authored 2 weeks ago
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Signed-off-by: Malte Munch <malte.munch@ltu.se>
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  2e3e4933
- bcdcheck2 added, assertions missing · 21ce1b8d
  Malte Munch authored 2 weeks ago
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Signed-off-by: Malte Munch <malte.munch@ltu.se>
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  21ce1b8d
- bcdcheck · e20e86e4
  Malte Munch authored 2 weeks ago
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Signed-off-by: Malte Munch <malte.munch@ltu.se>
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  e20e86e4
- init · e4ecc7ce
  Malte Munch authored 2 weeks ago
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Signed-off-by: Malte Munch <malte.munch@ltu.se>
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  e4ecc7ce