2023-11-11 16:53:32.005607468 +01:00:00 :start 13019, end 923173, diff 910154
2023-11-11 16:53:32.005607468 +01:00:00 :start 2027345902, end 2027385903, diff 40001
2023-11-11 16:53:32.005608851 +01:00:00 :idle
```
...
...
@@ -383,7 +383,7 @@ Now compare the measured cycle count, to the best case estimation (B5 above), wh
[Your answer here]
```
my best case estimate 30000 + 10000p fits with this if p is on the lower end at 1 cycle.
my best case estimate (relase build) 30000 + 10000p fits with this if p is on the lower end at 1 cycle.
```
Now, with a bit of luck the loop fits perfectly in the cache and you should not have any wait states triggered. However, the cache and pipeline fill is not very advanced/smart, so it depends largely on the address alignment. Try "moving" the loop by un-commenting one of the `asm::nop()` instructions. Re-run your application to see if the cycle count changed. Iterate, this (un-comment another) and try to find the "best" and "worst" case (lowest/highest number of cycles).