Peer review - Elias Olofsson

1. OK - Make sure the repo structure follows the original lab and that all files are present.

   I see no issues with the project structure.

2. Error - Do the unit test pass (asserts in the test bench).

   There is a syntax error in arith.veryl where the adder instantiation is missing a closing );, as well as one in logic.veryl where the case expression is missing a default case and a closing };. These errors are keeping the project from successfully building.

   After fixing these errors locally, the test for arith.veryl fails and after inspecting the code, it appears to be the adders b-input that is the issue. The input should be a 4-bit vector where every bit is the output of a XOR-operation between sub and the corresponding bit in the b-input of Arith. Currently, the input is a 4-bit vector where every bit is equal to sub.

   After fixing the adder input locally, all other tests passes.

3. Error - Part 1

   A. OK - Do the tables contain the correct values?

   Yes, the tables contain the correct vaules.

   B. Error - Has there been a discussion regarding the correctness and how we can detect errors using V or Cout for signed/unsigned? Is this discussion correct?

   There is an important pattern between the carry flag and another variable in the table for detecting errors with unsigned arithmetic, although the example operations in the table are not sufficient to find this pattern. For some reason, the authors have omitted an addition operation that causes an overflow for unsigned arithmetic (the forth example being an underflow), which is required to see this pattern. Try performing some unsigned addition operations around the upper limit (15) of a 4-bit unsigned number, as well as some subtractions around its lower limit (0), both causing and not causing over- and underflows, respectively.

4. OK - Is the full adder implemented correctly?

   Yes, it is implemented correctly.

5. OK - Is the 4-bit adder implemented correctly? Make sure the 4-bit adder is using 4 full adders (FULL_ADDER) as components.

   Yes, it is implemented correctly.

6. Error - Is the arithmetic unit implemented correctly? Make sure the arithmetic unit is using the 4-bit adder (ADDER) component.

   No, it has errors explained in point 2.

7. OK - Is the multiplexer implemented correctly? The mux should only change the output to a specific input depending on the OP code. The mux should have no other functionality (No AND/OR gates inside)

   There is no enforcement in the instructions of the Veryl version of the lab about having to implement logic.veryl using a separate mux module.

8. If no errors are found, suggest possible improvements.

   For future labs:

   1. Starting each line in a segment of markdown with a > turns that segment into a blockquote (like the answers in this issue). It's a nice way to make your answers stand out from the rest of the text.

   2. The Gitlab renderer of markdown files supports \LaTeX expressions within dollar signs that can add some beauty to boolean expressions.